always @(*) 和 assign 有区别吗

IC设计
1

从 verilog - always @(*) vs. assign - Electrical Engineering Stack Exchange的讨论来看是仅在time0的时候有区别，其他都是一样的。
对于共用一个条件的连接，always @(*)更容易控制

always @ (*)
  begin
    if(is_active == 0) begin
      master_if.psel  =          master_bind_if.psel;       
      master_if.penable  =       master_bind_if.penable;
      master_if.pwrite  =        master_bind_if.pwrite;             
      master_if.paddr   =        master_bind_if.paddr;      
      master_if.pwdata  =        master_bind_if.pwdata;     
      master_if.pstrb  =         master_bind_if.pstrb;       
      master_if.pprot  =         master_bind_if.pprot;       
      master_if.control_puser  = master_bind_if.control_puser;
    end
   end

从s家vip的代码来看，INCA和QUESTA在apb的这几个信号对assign的支持有问题，所以做了workaround，会进第一个分支，也就是用always @(*)，不知道是为什么

`ifdef SVT_MULTI_SIM_PROCEDURAL_COMBINATORIAL_DRIVE

  // input (Master Inputs)
  always @(*)
  begin
    master_if.prdata[0]    = master_bind_if.prdata;
    master_if.pready[0]    = master_bind_if.pready;
    master_if.pslverr[0]   = master_bind_if.pslverr;
  end
`else
   assign  master_if.prdata[0]     = master_bind_if.prdata; 
   assign  master_if.pready[0]     = master_bind_if.pready;
   assign  master_if.pslverr[0]    = master_bind_if.pslverr;
`endif